A dynamic 1-transistor memory cell may comprise a storage element to store data and an access device to access the data stored in the storage element. The storage element may be a storage capacitor, a magnetoresistive element, a ferroelectric element of a phase-change element. Data may be stored by charging or discharging the storage capacitor.
The access device is typically a field-effect transistor (FET). An active area of the access transistor is formed in a single crystalline semiconductor substrate such as a silicon wafer. The active area comprises a first impurity region defining a source region, a second impurity region defining a drain region and a channel region being in contact with both the first and the second source/drain-region. The first and the second impurity regions have a first conductivity type. The channel region may have a second conductivity type that is the opposite of the first conductivity type.
The first impurity region may be connected to a storage node electrode of a storage capacitor. The second impurity region is connected to a bit line, which transmits data to and from the memory cell. The access transistor is controlled by a voltage applied to its gate electrode, which, for planar transistor devices, is arranged above a pattern surface of the substrate and which is adjacent to the respective channel section. A gate dielectric insulates the gate electrode from the channel region. The electric potential of the gate electrode controls the charge carrier distribution in the adjoining channel section by capacitive coupling. The gate electrodes of the access transistors of a plurality of memory cells are connected and form a connection line (word line) for addressing a row of memory cells within a memory cell array.
Applying a voltage higher than the threshold voltage to the gate electrode induces an inversion zone of mobile charge carriers in the channel section, where the charge carriers form a conductive channel in the channel section between the two impurity regions. The conductive channel connects the storage node electrode of the capacitor to the bit line. Applying a voltage lower than the threshold voltage to the gate electrode separates the storage node electrode from the bit line. At channel lengths below 400 nanometers, short channel effects occur.
A recessed channel array transistor (RCAT) or 3D-channel field-effect transistor with enhanced effective channel length provides a gate electrode arranged in a gate groove that is etched into the semiconductor substrate between the source and the drain region. A gate dielectric extends along the semiconductor sidewalls of the gate groove and separates the gate electrode and the channel region. In the inversion state, the channel extends in a first vertical section from the source region downward along the first sidewall of the gate groove, crosses beneath the gate groove in essentially horizontal direction and extends then in a second vertical section along a second sidewall of the gate groove upward to the drain region. The effective channel length of a RCAT is a function of the depth of the gate groove and the planar distance between the source and the drain region.
At maximum packaging density, the effective channel width of a RCAT is defined through the minimum lithographic feature size. The effective channel width corresponds to the resistance of the transistor in the conducting state (Ron) and determines the switching characteristics of the memory cell. An extended U-groove transistor with corner gate device (EUD) comprises a gate electrode with corner sections that partly wrap around an edge of a semiconductor lamella that comprises at least a section of the channel region. Near the edge, the electrical fields act on the channel region from two different directions resulting in improved transistor properties.
The corner sections of the gate electrode may extend along further sections of the vertical sidewalls of the semiconductor lamella, wherein, in the inversion state, the channel is formed both along the sidewalls of the gate groove and along sections of the sidewalls on the long sides of the semiconductor lamella. The channel width is increased by the portion of the channel that extends along the sidewalls of the semiconductor lamella. Due to the corners and the increased channel width, EUDs show a low Ron and fast switching characteristics.
A need exists for 3D-channel field-effect transistors with further enhanced switching characteristics.